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±15kV ESD-Protected Touch-Screen
Controllers Include DAC and Keypad Controller
ELECTRICAL CHARACTERISTICS (continued)
(DV DD = AV DD = +2.7V to +3.6V (MAX1233), DV DD = AV DD = +4.75V to +5.25V (MAX1234), external reference V REF = 2.5V
(MAX1233), V REF = 4.096V (MAX1234); f SCLK = 10MHz, f SAMPLE = 50ksps, 12-bit mode, 0.1μF capacitor at REF, T A = -40°C to
+85°C, unless otherwise noted. Typical values are at T A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
C IN
15
pF
DIGITAL OUTPUT (DOUT)
Output Voltage Low
Output Voltage High
V OL
V OH
I SINK = 2mA
I SINK = 4mA
I SOURCE = 1.5mA
DV DD -
0.5
0.4
0.8
V
V
DIGITAL OUTPUT ( BUSY , PENIR Q , KEYIRQ , R_, C_)
Output Voltage Low
Output Voltage High
V OL
V OH
I SINK = 0.2mA
I SOURCE = 0.2mA
DV DD -
0.5
0.4
V
V
POWER REQUIREMENTS
Supply Voltage (Note 12)
AV DD /
DV DD
MAX1233
MAX1234
2.7
4.75
3
5
3.6
5.25
V
Idle; all blocks shut down
0.5
5
Analog and Digital Supply
Current
I AVDD +
I DVDD
Only ADC on; f SAMPLE = 20ksps
Only DAC on; no load
150
150
500
230
μA
TIMING CHARACTERISTICS
Only internal reference on
670
900
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
t CP
t CH
t CL
t DS
t DH
100
40
40
40
0
ns
ns
ns
ns
ns
SCLK Fall to DOUT Valid
CS Fall to DOUT Enabled
CS Rise to DOUT Disabled
CS Fall to SCLK Rise
CS Fall to SCLK Ignored
SCLK Rise to R_/C_ Data Valid
CS Pulse Width High
t DOV
t DV
t DOD
t CSS
t CSH
t GPO
t CSW
C LOAD = 50pF
C LOAD = 50pF
C LOAD = 50pF
C LOAD = 50pF (Note 13)
40
0
40
40
45
40
230
ns
ns
ns
ns
ns
ns
ns
Note 1: Tested at DV DD = AV DD = +2.7V (MAX1233), DV DD = AV DD = +5V (MAX1234).
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the offset and gain errors
have been removed.
Note 3: Offset nulled.
Note 4: Difference between TEMP1 and TEMP2; temperature in °K = (V TEMP2 - V TEMP1 ) × 2680°K/V. No calibration is necessary.
Note 5: Temperature coefficient is -2.1mV/°C. Determine absolute temperature by extrapolating from a calibrated value.
Note 6: ADC performance is limited by the conversion noise floor, typically 300μV P-P . An external reference below 2.5V can
compromise the ADC performance.
Note 7: Guaranteed from code 5 to 255.
_______________________________________________________________________________________
5
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